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| 80C186EC 80C188EC AND 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSORS X Fully Static Operation X True CMOS Inputs and Outputs Y Y Speed Version Available (3V) 16 MHz (80L186EC16 80L188EC16) 13 MHz (80L186EC13 80L188EC13) Y Direct Addressing Capability to 1 Mbyte Memory and 64 Kbyte I O Low-Power Operating Modes Idle Mode Freezes CPU Clocks but Keeps Peripherals Active Powerdown Mode Freezes All Internal Clocks Powersave Mode Divides All Clocks by Programmable Prescalar Y The 80C186EC is a member of the 186 Integrated Processor Family The 186 Integrated Processor Family incorporates several different VLSI devices all of which share a common CPU architecture the 8086 8088 The 80C186EC uses the latest high density CHMOS technology to integrate several of the most common system peripherals with an enhanced 8086 CPU core to create a powerful system on a single monolithic silicon die w w Other brands and names are the property of their respective owners Information in this document is provided in connection with Intel products Intel assumes no liability whatsoever including infringement of any patent or copyright for sale and use of Intel products except as provided in Intel's Terms and Conditions of Sale for such products Intel retains the right to make changes to these specifications at any time without notice Microcomputer Products may have minor variations to this specification known as errata COPYRIGHT (c) INTEL CORPORATION, 2004 August, 2004 Order Number: 272434-006 w .d sh ta a 4u et e om .c www..com Integrated Feature Set Low-Power Static Enhanced 8086 CPU Core Two Independent DMA Supported UARTs each with an Integral Baud Rate Generator Four Independent DMA Channels 22 Multiplexed I O Port Pins Two 8259A Compatible Programmable Interrupt Controllers Three Programmable 16-Bit Timer Counters 32-Bit Watchdog Timer Ten Programmable Chip Selects with Integral Wait-State Generator Memory Refresh Control Unit Power Management Unit On-Chip Oscillator System Level Testing Support (ONCE Mode) Y Available in Extended Temperature Range ( b 40 C to a 85 C) Supports 80C187 Numerics Processor Extension (80C186EC only) Package Types 100-Pin EIAJ Quad Flat Pack (QFP) 100-Pin Plastic Quad Flat Pack (PQFP) 100-Pin Shrink Quad Flat Pack (SQFP) Speed Versions Available (5V) 25 MHz (80C186EC25 80C188EC25) 20 MHz (80C186EC20 80C188EC20) 13 MHz (80C186EC13 80C188EC13) Y Y Y 80C186EC 80C188EC and 80L186EC 80L188EC 16-BIT HIGH-INTEGRATION EMBEDDED PROCESSOR CONTENTS INTRODUCTION 80C186EC CORE ARCHITECTURE Bus Interface Unit Clock Generator 80C186EC PERIPHERAL ARCHITECTURE Programmable Interrupt Controllers Timer Counter Unit Serial Communications Unit DMA Unit Chip-Select Unit I O Port Unit Refresh Control Unit Watchdog Timer Unit Power Management Unit 80C187 Interface (80C186EC only) ONCE Test Mode PACKAGE INFORMATION Prefix Identification Pin Descriptions Pinout Package Thermal Specifications ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings PAGE 4 4 4 4 5 7 7 7 7 7 7 7 7 8 8 8 8 8 8 15 24 25 25 CONTENTS Recommended Connections DC SPECIFICATIONS ICC versus Frequency and Voltage PDTMR Pin Delay Calculation AC SPECIFICATIONS AC Characteristics 80C186EC25 AC Characteristics 80C186EC20 13 AC Characteristics 80L186EC13 AC Characteristics 80L186EC16 Relative Timings Serial Port Mode 0 Timings AC TEST CONDITIONS AC TIMING WAVEFORMS DERATING CURVES RESET BUS CYCLE WAVEFORMS EXECUTION TIMINGS INSTRUCTION SET SUMMARY ERRATA REVISION HISTORY PAGE 25 26 29 29 30 30 32 33 34 35 36 37 37 40 40 43 50 51 57 57 2 80C186EC 188EC 80L186EC 188EC 272434 - 1 NOTE Pin names in parentheses apply to the 80C188EC 80L188EC Figure 1 80C186EC 80L186EC Block Diagram 3 80C186EC 188EC 80L186EC 188EC INTRODUCTION Unless specifically noted all references to the 80C186EC apply to the 80C188EC 80L186EC and 80L188EC References to pins that differ between the 80C186EC 80L186EC and the 80C188EC 80L188EC are given in parentheses The ``L'' in the part number denotes low voltage operation Physically and functionally the ``C'' and ``L'' devices are identical The 80C186EC is one of the highest integration members of the 186 Integrated Processor Family Two serial ports are provided for services such as interprocessor communication diagnostics and modem interfacing Four DMA channels allow for high speed data movement as well as support of the onboard serial ports A flexible chip select unit simplifies memory and peripheral interfacing The three general purpose timer counters can be used for a variety of time measurement and waveform generation tasks A watchdog timer is provided to insure system integrity even in the most hostile of environments Two 8259A compatible interrupt controllers handle internal interrupts and up to 57 external interrupt requests A DRAM refresh unit and 24 multiplexed I O ports round out the feature set of the 80C186EC The future set of the 80C186EC meets the needs of low-power space-critical applications Low-power applications benefit from the static design of the CPU and the integrated peripherals as well as low voltage operation Minimum current consumption is achieved by providing a powerdown mode that halts operaton of the device and freezes the clock circuits Peripheral design enhancements ensure that non-initialized peripherals consume little current The 80L186EC is the 3V version of the 80C186EC The 80L186EC is functionally identical to the 80C186EC embedded processor Current 80C186EC users can easily upgrade their designs to use the 80L186EC and benefit from the reduced power consumption inherent in 3V operation Figure 1 shows a block diagram of the 80C186EC 80C188EC The execution unit (EU) is an enhanced 8086 CPU core that includes dedicated hardware to speed up effective address calculations enhanced execution speed for multiple-bit shift and rotate instructions and for multiply and divide instructions string move instructions that operate at full bus bandwidth ten new instructions and fully static operation The bus interface unit (BIU) is the same as that found on the original 186 family products except the queue-status mode has been deleted and buffer interface control has been changed to ease system design timings An independent internal bus is used for communication between the BIU and onchip peripherals 4 80C186EC CORE ARCHITECTURE Bus Interface Unit The 80C186EC core incorporates a bus controller that generates local bus control signals In addition it employs a HOLD HLDA protocol to share the local bus with other bus masters The bus controller is responsible for generating 20 bits of address read and write strobes bus cycle status information and data (for write operations) information It is also responsible for reading data from the local bus during a read operation A ready input pin is provided to extend a bus cycle beyond the minimum four states (clocks) The bus controller also generates two control signals (DEN and DT R) when interfacing to external transceiver chips This capability allows the addition of transceivers for simple buffering of the multiplexed address data bus Clock Generator The 80C186EC provides an on-chip clock generator for both internal and external clock generation The clock generator features a crystal oscillator a divideby-two counter and three low-power operating modes The oscillator circuit is designed to be used with either a parallel resonant fundamental or third-overtone mode crystal network Alternatively the oscillator circuit may be driven from an external clock source Figure 2 shows the various operating modes of the oscillator circuit The crystal or clock frequency chosen must be twice the required processor operating frequency due to the internal divide-by-two counter This counter is used to drive all internal phase clocks and the external CLKOUT signal CLKOUT is a 50% duty cycle processor clock and can be used to drive other system components All AC timings are referenced to CLKOUT The following parameters are recommended when choosing a crystal Temperature Range Application Specific ESR (Equivalent Series Res ) 40X max C0 (Shunt Capacitance of Crystal) 7 0 pF max CL (Load Capacitance) 20 pF g2 pF Drive Level 1 mW (max) 80C186EC 188EC 80L186EC 188EC 272434 - 2 NOTE 1 The LC network is only required when using a third overtone crystal Figure 2 80C186EC Clock Connections 80C186EC PERIPHERAL ARCHITECTURE The 80C186EC integrates several common system peripherals with a CPU core to create a compact yet powerful system The integrated peripherals are designed to be flexbile and provide logical interconnections between supporting units (e g the DMA unit can accept requests from the Serial Communications Unit) The list of integrated peripherals includes Two cascaded 8259A compatible Programmable Interrupt Controllers 3-Channel Timer Counter Unit 2-Channel Serial Communications Unit 4-Channel DMA Unit 10-Output Chip-Select Unit 32-bit Watchdog Timer Unit I O Port Unit Refresh Control Unit Power Management Unit The registers associated with each integrated peripheral are contained within a 128 x 16-bit register file called the Peripheral Control Block (PCB) The base address of the PCB is programmable and can be located on any 256 byte address boundary in either memory or I O space Figure 3 provides a list of the registers associated with the PCB The Register Bit Summary individually lists all of the registers and identifies each of their programming attributes 5 80C186EC 188EC 80L186EC 188EC PCB Offset 00H 02H 04H 06H 08H 0AH 0CH 0EH 10H 12H 14H 16H 18H 1AH 1CH 1EH 20H 22H 24H 26H 28H 2AH 2CH 2EH 30H 32H 34H 46H 38H 3AH 3CH 3EH Function Master PIC Port 0 Master PIC Port 1 Slave PIC Port 0 Slave PIC Port 1 Reserved SCU Int Req Ltch DMA Int Req Ltch TCU Int Req Ltch Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved WDT Reload High WDT Reload Low WDT Count High WDT Count Low WDT Clear WDT Disable Reserved Reserved T0 Count T0 Compare A T0 Compare B T0 Control T1 Count T1 Compare A T1 Compare B T1 Control PCB Offset 40H 42H 44H 46H 48H 4AH 4CH 4EH 50H 52H 54H 56H 58H 5AH 5CH 5EH 60H 62H 64H 66H 68H 6AH 6CH 6EH 70H 72H 74H 76H 78H 7AH 7CH 7EH Function T2 Count T2 Compare Reserved T2 Control Port 3 Direction Port 3 Pin State Port 3 Mux Control Port 3 Data Latch Port 1 Direction Port 1 Pin State Port 1 Mux Control Port 1 Data Latch Port 2 Direction Port 2 Pin State Port 2 Mux Control Port 2 Data Latch SCU 0 Baud SCU 0 Count SCU 0 Control SCU 0 Status SCU 0 RBUF SCU 0 TBUF Reserved Reserved SCU 1 Baud SCU 1 Count SCU 1 Control SCU 1 Status SCU 1 RBUF SCU 1 TBUF Reserved Reserved PCB Offset 80H 82H 84H 86H 88H 8AH 8CH 8EH 90H 92H 94H 96H 98H 9AH 9CH 9EH A0H A2H A4H A6H A8H AAH ACH AEH B0H B2H B4H B6H B8H BAH BCH BEH Function GCS0 Start GCS0 Stop GCS1 Start GCS1 Stop GCS2 Start GCS2 Stop GCS3 Start GCS3 Stop GCS4 Start GCS4 Stop GCS5 Start GCS5 Stop GCS6 Start GCS6 Stop GCS7 Start GCS7 Stop LCS Start LCS Stop UCS Start UCS Stop Relocation Register Reserved Reserved Reserved Refresh Base Addr Refresh Time Refresh Control Refresh Address Power Control Reserved Step ID Powersave PCB Offset C0H C2H C4H C6H C8H CAH CCH CEH D0H D2H D4H D6H D8H DAH DCH DEH E0H E2H E4H E6H E8H EAH ECH EEH F0H F2H F4H F6H F8H FAH FCH FEH Function DMA 0 Source Low DMA 0 Source High DMA 0 Dest Low DMA 0 Dest High DMA 0 Count DMA 0 Control DMA Module Pri DMA Halt DMA 1 Source Low DMA 1 Source High DMA 1 Dest Low DMA 1 Dest High DMA 1 Count DMA 1 Control Reserved Reserved DMA 2 Source Low DMA 2 Source High DMA 2 Dest Low DMA 2 Dest High DMA 2 Count DMA 2 Control Reserved Reserved DMA 3 Source Low DMA 3 Source High DMA 3 Dest Low DMA 3 Dest High DMA 3 Count DMA 3 Control Reserved Reserved Figure 3 Peripheral Control Block Registers 6 80C186EC 188EC 80L186EC 188EC DMA requests can be external (on the DRQ pins) internal (from Timer 2 or a serial channel) or software initiated The DMA Unit transfers data as bytes only Each data transfer requires at least two bus cycles one to fetch data and one to deposit The minimum clock count for each transfer is 8 but this will vary depending on synchronization and wait states Programmable Interrupt Controllers The 80C186EC utilizes two 8259A compatible Programmable Interrupt Controllers (PIC) to manage both internal and external interrupts The 8259A modules are configured in a master slave arrangement Seven of the external interrupt pins INT0 through INT6 are connected to the master 8259A module The eighth external interrupt pin INT7 is connected to the slave 8259A module There are a total of 11 internal interrupt sources from the integrated peripherals 4 Serial 4 DMA and 3 Timer Counter Chip-Select Unit The 80C186EC Chip-Select Unit (CSU) integrates logic which provides up to ten programmable chipselects to access both memories and peripherals In addition each chip-select can be programmed to automatically insert additional clocks (wait states) into the current bus cycle and or automatically terminate a bus cycle independent of the condition of the READY input pin Timer Counter Unit The 80C186EC Timer Counter Unit (TCU) provides three 16-bit programmable timers Two of these are highly flexible and are connected to external pins for external control or clocking The third timer is not connected to any external pins and can only be clocked internally However it can be used to clock the other two timer channels The TCU can be used to count external events time external events generate non-repetitive waveforms or generate timed interrupts I O Port Unit The I O Port Unit on the 80C186EC supports two 8-bit channels and one 6-bit channel of input output or input output operation Port 1 is multiplexed with the chip select pins and is output only Port 2 is multiplexed with the pins for serial channels 1 and 2 All Port 2 pins are input output Port 3 has a total of 6 pins four that are multiplexed with DMA and serial port interrupts and two that are non-multiplexed open drain I O Serial Communications Unit The 80C186EC Serial Communications Unit (SCU) contains two independent channels Each channel is identical in operation except that only channel 0 is directly supported by the integrated interrupt controller (the channel 1 interrupts are routed to external interrupt pins) Each channel has its own baud rate generator and can be internally or externally clocked up to one half the processor operating frequency Both serial channels can request service from the DMA unit thus providing block reception and transmission without CPU intervention Independent baud rate generators are provided for each of the serial channels For the asynchronous modes the generator supplies an 8x baud clock to both the receive and transmit shifting register logic A 1x baud clock is provided in the synchronous mode Refresh Control Unit The Refresh Control Unit (RCU) automatically generates a periodic memory read bus cycle to keep dynamic or pseudo-static memory refreshed A 9-bit counter controls the number of clocks between refresh requests A 12-bit address generator is maintained by the RCU and is presented on the A12 1 address lines during the refresh bus cycle Address bits A19 13 are programmable to allow the refresh address block to be located on any 8 Kbyte boundary Watchdog Timer Unit The Watchdog Timer Unit (WDT) allows for graceful recovery from unexpected hardware and software upsets The WDT consists of a 32-bit counter that decrements every clock cycle If the counter reaches zero before being reset the WDTOUT pin is DMA Unit The four channel Direct Memory Access (DMA) Unit is comprised of two modules with two channels each All four channels are identical in operation DMA transfers can take place from memory to memory I O to memory memory to I O or I O to I O 7 80C186EC/188EC, 80L186EC/188EC pulled low for four clock cycles. Logically ANDing the WDTOUT pin with the power-on reset signal allows the WDT to reset the device in the event of a WDT timeout. If a less drastic method of recovery is desired. WDTOUT can be connected directly to NMI or one of the INT input pins. The WDT may also be used as a general purpose timer. and information, see the Intel Packaging Outlines and Dimensions Guide (Order Number: 231369). Prefix Identification Table 1 lists the prefix identifications. Table 1: Prefix Identification Prefix Note Package Type PQFP SQFP Temperature Range Extended/Commercial Extended/Commercial Power Management Unit The 80C186EC Power Management Unit (PMU) is provided to control the power consumption of the device. The PMU provides four power management modes: Active, Powersave, Idle and Powerdown. Active Mode indicates that all units on the 80C186EC are operating at 1/2 the CLKIN frequency. Idle Mode freezes the clocks of the Execution and Bus units at a logic zero state (all peripherals continue to operate normally). The Powerdown Mode freezes all internal clocks at a logic zero level and disables the crystal oscillator. In Powersave Mode, all internal clock signals are divided by a programmable prescalar (up to 1/64 the normal frequency). Powersave Mode can be used with Idle Mode as well as during normal (Active Mode) operation. x x x x 1 1 1 QFP (EIAJ) Extended QFP (EIAJ) Commercial NOTE: 1. The 5V 25 MHz version is only available in commercial temperature range corresponding to 0 C to a 70 C ambient. 1. To address the fact that many of the package prefix variables have changed, all package prefix variables in this document are now indicated with an "x". Pin Descriptions Each pin or logical set of pins is described in Table 2, There are four columns for each entry in the Pin Description Table. The following sections describe each column. Column 1. Pin Name In this column is a mnemonic that describes the pin function. Negation of the signal name (i.e. RESIN) implies that the signal is active low. Column 2. Pin Type A pin may be either power (P), ground (G), input only (I), output only (O) or input/output (I/O). Please note that some pins have more than 1 function. A19/S6/ONCE , for example, is normally an output but functions as an input durreset. For this reason ing A19/S6/ONCE is classified as an input/ output pin. Column 3. Input Type (for I and I/O types only) There are two different types of input pins on the 80C186EC: asynchronous and synchronous. Asynchronous pins require that setup and hold times be met only to guarantee recognition . Synchronous input pins require that the setup and hold times be met to guarantee proper operation . Stated simply, missing a setup or hold on an asynchronous pin will result in something minor (i.e. a timer count will be missed) whereas missing a setup or hold on a synchronous pin will result in system failure (the system will ``lock up''). An input pin may also be edge or level sensitive. 80C187 Interface (80C186EC only) The 80C186EC supports the direct connection of the 80C187 Numerics Processor Extension. The 80C187 can dramatically improve the performance of calculation intensive applications. ONCE Test Mode To facilitate testing and inspection of devices when fixed into a target system, the 80C186EC has a test mode available which forces all output and input/ output pins to be placed in the high-impedance state. ONCE stands for ``ON Circuit Emulation'', The ONCE mode is selected by forcing the A19/S6/ONCE pin low during a processor reset (this pin is weakly held high during reset to prevent inadvertant entrance into ONCE Mode). PACKAGE INFORMATION This section describes the pin functions, pinout and thermal characteristics for the 80C186EC in the Plastic Quad Flat Pack (JEDEC PQFP), the EIAJ Quad Flat Pack (QFP) and the Shrink Quad Flat Pack (SQFP). For complete package specifications 8 80C186EC 188EC 80L186EC 188EC Column 4 Output States (for O and I O types only) The state of an output or I O pin is dependent on the operating mode of the device There are four modes of operation that are different from normal active mode Bus Hold Reset Idle Mode Powerdown Mode This column describes the output pin state in each of these modes The legend for interpreting the information in the Pin Descriptions is shown in Table 1 As an example please refer to the table entry for AD12 0 The ``I O'' signifies that the pins are bidirectional (i e have both an input and output function) The ``S'' indicates that as an input the signal must be synchronized to CLKOUT for proper operation The ``H(Z)'' indicates that these pins will float while the processor is in the Hold Acknowledge state R(Z) indicates that these pins will float while RESIN is low P(0) and I(0) indicate that these pins will drive 0 when the device is in either Powerdown or Idle Mode Some pins the I O Ports for example can be programmed to perform more than one function Multifunction pins have a `` '' in their signal name between the different functions (i e P3 0 RXI1) If the input pin type or output pin state differ between functions then that will be indicated by separating the state (or type) with a `` '' (i e H(X) H(Q)) In this example when the pin is configured as P3 0 then its hold output state is H(X) when configured as RXI1 its output state is H(Q) All pins float while the processor is in the ONCE Mode (with the exception of OSCOUT) Table 1 Pin Description Nomenclature Symbol P G I O IO S(E) S(L) A(E) A(L) H(1) H(0) H(Z) H(Q) H(X) R(WH) R(1) R(0) R(Z) R(Q) R(X) I(1) I(0) I(Z) I(Q) I(X) P(1) P(0) P(Z) P(Q) P(X) Description Power Pin (apply a VCC voltage) Ground (connect to VSS) Input only pin Output only pin Input Output pin Synchronous edge sensitive Synchronous level sensitive Asynchronous edge sensitive Asynchronous level sensitive Output driven to VCC during bus hold Output driven to VSS during bus hold Output floats during bus hold Output remains active during bus hold Output retains current state during bus hold Output weakly held at VCC during reset Output driven to VCC during reset Output driven to VSS during reset Output floats during reset Output remains active during reset Output retains current state during reset Output driven to VCC during Idle Mode Output driven to VSS during Idle Mode Output floats during Idle Mode Output remains active during Idle Mode Output retains current state during Idle Mode Output driven to VCC during Powerdown Mode Output driven to VSS during Powerdown Mode Output floats during Powerdown Mode Output remains active during Powerdown Mode Output retains current state during Powerdown Mode 9 80C186EC 188EC 80L186EC 188EC Table 2 Pin Descriptions Pin Name VCC VSS CLKIN Pin Type P G I A(E) Input Type Output States GROUND CLocK INput is the external clock input An external oscillator operating at two times the required processor operating frequency can be connected to CLKIN For crystal operation CLKIN (along with OSCOUT) are the crystal connections to an internal Pierce oscillator H(Q) R(Q) I(Q) P(X) OSCillator OUTput is only used when using a crystal to generate the internal clock OSCOUT (along with CLKIN) are the crystal connections to an internal Pierce oscillator This pin can not be used as 2X clock output for noncrystal applications (i e this pin is not connected for noncrystal applications) CLocK OUTput provides a timing reference for inputs and outputs of the processor and is one-half the input clock (CLKIN) frequency CLKOUT has a 50% duty cycle and transitions every falling edge of CLKIN RESet IN causes the processor to immediately terminate any bus cycle in progress and assume an initialized state All pins will be driven to a known state and RESOUT will also be driven active The rising edge (low-to-high) transition synchronizes CLKOUT with CLKIN before the processor begins fetching opcodes at memory location 0FFFF0H H(0) R(1) I(0) P(0) A(L) H(WH) R(Z) P(WH) I(WH) RESet OUTput that indicates the processor is currently in the reset state RESOUT will remain active as long as RESIN remains active Power-Down TiMeR pin (normally connected to an external capacitor) that determines the amount of time the processors waits after an exit from Powerdown before resuming normal operation The duration of time required will depend on the startup characteristics of the crystal oscillator Non-Maskable Interrupt input causes a TYPE-2 interrupt to be serviced by the CPU NMI is latched internally TEST is used during the execution of the WAIT instruction to suspend CPU operation until the pin is sampled active (LOW) TEST is alternately known as BUSY when interfacing with an 80C187 numerics coprocessor (80C186EC only) H(Z) R(WH) I(0) P(0) This pin drives address bit 19 during the address phase of the bus cycle During T2 and T3 this pin functions as status bit 6 S6 is low to indicate CPU bus cycles and high to indicate DMA or refresh bus cycles During a processor reset (RESIN active) this pin becomes the ONCE input pin Holding this pin low during reset will force the part into ONCE Mode Pin Description POWER a 5V g10% power supply connection OSCOUT O CLKOUT O H(Q) R(Q) I(Q) P(X) A(L) RESIN I RESOUT O PDTMR IO NMI TEST BUSY (TEST) I I A(E) A(E) A19 S6 ONCE IO A(L) NOTE Pin names in parentheses apply to the 80C188EC 80L188EC 10 80C186EC 188EC 80L186EC 188EC Table 2 Pin Descriptions (Continued) Pin Name A18 S5 A17 S4 A16 S3 (A15 8) Pin Type IO Input Type A(L) Output States H(Z) R(WH) I(0) P(0) Pin Description These pins drive address information during the address phase of the bus cycle During T2 and T3 these pins drive status information (which is always 0 on the 80C186EC) These pins are used as inputs during factory test driving these pins low during reset will cause unspecified operation On the 80C188EC A15 8 provide valid address information for the entire bus cycle These pins are part of the multiplexed ADDRESS and DATA bus During the address phase of the bus cycle address bits 15 through 13 are presented on these pins and can be latched using ALE Data information is transferred during the data phase of the bus cycle Pins AD15 13 CAS2 0 drive the 82C59 slave address information during interrupt acknowledge cycles These pins provide a multiplexed ADDRESS and DATA bus During the address phase of the bus cycle address bits 0 through 12 (0 through 7 on the 80C188EC) are presented on the bus and can be latched using ALE Data information is transferred during the data phase of the bus cycle Bus cycle Status are encoded on these pins to provide bus transaction information S2 0 are encoded as follows S2 0 0 0 0 1 1 1 1 ALE O H(0) R(0) I(0) P(0) H(Z) R(Z) I(1) P(1) S1 0 0 1 1 0 0 1 1 S0 0 1 0 1 0 1 0 1 Bus Cycle Initiated Interrupt Acknowledge Read I O Write I O Processor HALT Instruction Queue Fetch Read Memory Write Memory Passive (No bus activity) AD15 CAS2 AD14 CAS1 AD13 CAS0 IO S(L) H(Z) R(Z) I(0) P(0) AD12 0 (AD7 0) IO S(L) H(Z) R(Z) I(0) P(0) H(Z) R(1) I(1) P(1) S2 0 O Address Latch Enable output is used to strobe address information into a transparent type latch during the address phase of the bus cycle Byte High Enable output to indicate that the bus cycle in progress is transferring data over the upper half of the data bus BHE and A0 have the following logical encoding Encoding (for 80C186EC 80L186EC only) Word transfer Even Byte transfer Odd Byte transfer Refresh operation BHE (RFSH) O A0 0 0 1 1 BHE 0 1 0 1 On the 80C188EC 80L188EC RFSH is asserted low to indicate a refresh bus cycle NOTE Pin names in parentheses apply to the 80C188EC 80L188EC 11 80C186EC 188EC 80L186EC 188EC Table 2 Pin Descriptions (Continued) Pin Name RD Pin Type O Input Type Output States H(Z) R(Z) I(1) P(1) H(Z) R(Z) I(1) P(1) A(L) S(L) (Note 1) H(Z) R(Z) I(1) P(1) H(Z) R(Z) I(X) P(X) A(L) H(Z) R(Z) I(X) P(X) Pin Description ReaD output signals that the accessed memory or I O device should drive data information onto the data bus WR O WRite output signals that data available on the data bus are to be written into the accessed memory or I O device READY I READY input to signal the completion of a bus cycle READY must be active to terminate any 80C186EC bus cycle unless it is ignored by correctly programming the Chip-Select unit Data ENable output to control the enable of bi-directional transceivers in a buffered system DEN is active only when data is to be transferred on the bus Data Transmit Receive output controls the direction of a bidirectional buffer in a buffered system DEN O DT R O LOCK IO LOCK output indicates that the bus cycle in progress is not interruptable The processor will not service other bus requests (such as HOLD) while LOCK is active This pin is configured as a weakly held high input while RESIN is active and must not be driven low HOLD request input to signal that an external bus master wishes to gain control of the local bus The processor will relinquish control of the local bus between instruction boundaries that are not LOCKed HOLD I A(L) HLDA O H(1) R(0) I(0) P(0) H(1) R(1) I(1) P(1) A(L) HoLD Acknowledge output to indicate that the processor has relinquished control of the local bus When HLDA is asserted the processor will (or has) floated its data bus and control signals allowing another bus master to drive the signals directly Numerics Coprocessor Select output is generated when acessing a numerics coprocessor This signal does not exist on the 80C188EC 80L188EC ERROR input that indicates the last numerics processor extension operation resulted in an exception condition An interrupt TYPE 16 is generated if ERROR is sampled active at the beginning of a numerics operation Systems not using an 80C187 must tie ERROR to VCC This signal does not exist on the 80C188EC 80L188EC NCS O ERROR I NOTE Pin names in parentheses apply to the 80C188EC 80L188EC 12 80C186EC 188EC 80L186EC 188EC Table 2 Pin Descriptions (Continued) Pin Name PEREQ Pin Type I Input Type A(L) Output States Pin Description Processor Extension REQuest signals that a data transfer between an 80C187 Numerics Processor Extension and Memory is pending Systems not using an 80C187 must tie this pin to VSS This signal does not exist on the 80C188EC 80L188EC H(1) R(1) I(1) P(1) H(1) R(1) I(1) P(1) H(X) H(1) R(1) I(X) I(1) P(X) P(1) Upper Chip Select will go active whenever the address of a memory or I O bus cycle is within the address range programmed by the user After reset UCS is configured to be active for memory accesses between 0FFC00H and 0FFFFFH Lower Chip Select will go active whenever the address of a memory or I O bus cycle is within the address range programmed by the user LCS is inactive after a reset These pins provide a multiplexed function If enabled each pin can provide a General purpose Chip Select output which will go active whenever the address of a memory or I O bus cycle is within the address limitations programmed by the user When not programmed as a Chip-Select each pin may be used as a general purpose output port UCS O LCS O P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 GCS0 GCS1 GCS2 GCS3 GCS4 GCS5 GCS6 GCS7 O T0OUT T1OUT O H(Q) R(1) I(Q) P(X) A(L) A(E) Timer OUTput pins can be programmed to provide single clock or continuous waveform generation depending on the timer mode selected Timer INput is used either as clock or control signals depending on the timer mode selected This pin may be either level or edge sensitive depending on the programming mode Maskable INTerrupt input will cause a vector to a specific Type interrupt routine The INT6 0 pins can be used as cascade inputs from slave 8259A devices The INT pins can be configured as level or edge sensitive T0IN T1IN I INT7 0 I A(L) A(E) INTA O H(1) R(1) I(1) P(1) A(L) H(X) R(Z) I(X) H(X) H(X) R(0) I(Q) P(X) INTerrupt Acknowledge output is a handshaking signal used by external 82C59A Programmable Interrupt Controllers Bidirectional open-drain port pins P3 5 P3 4 IO P3 3 DMAI1 P3 2 DMAI0 O DMA Interrupt output goes active to indicate that the channel has completed a transfer DMAI1 and DMAI0 are multiplexed with output only port functions NOTE Pin names in parentheses apply to the 80C188EC 80L188EC 13 80C186EC 188EC 80L186EC 188EC Table 2 Pin Descriptions (Continued) Pin Name P3 1 TXI1 Pin Type O Input Type Output States H(X) H(Q) R(0) I(Q) P(X) H(X) H(Q) R(0) I(Q) P(X) H(Q) R(1) I(Q) P(X) A(L) H(X) R(Z) I(X) P(X) H(X) R(Z) I(X) P(X) H(Q) R(Z) I(X) I(Q) P(X) H(X) H(Q) R(Z) I(X) I(Q) P(X) Pin Description Transmit Interrupt output goes active to indicate that serial channel 1 has completed a transfer TXI1 is multiplexed with an output only Port function Receive Interrupt output goes active to indicate that serial channel 1 has completed a reception RXI1 is multiplexed with an output only port function WatchDog Timer OUTput is driven low for four clock cycles when the watchdog timer reaches zero WDTOUT may be ANDed with the power-on reset signal to reset the processor when the watchdog timer is not properly reset Clear-To-Send input is used to prevent the transmission of serial data on the TXD signal pin CTS1 and CTS0 are multiplexed with an I O Port function Baud CLocK input can be used as an alternate clock source for each of the integrated serial channels The BCLK inputs are multiplexed with I O Port functions The BCLK input frequency cannot exceed the operating frequency of the processor Transmit Data output provides serial data information The TXD outputs are multiplexed with I O Port functions During synchronous serial communications TXD will function as a clock output Receive Data input accepts serial data information The RXD pins are multiplexed with I O Port functions During synchronous serial communications RXD is bi-directional and will become an output for transmission of data (TXD becomes the clock) DMA ReQuest input pins are used to request a DMA transfer The timing of the request is dependent on the programmed synchronization mode P3 0 RXI1 O WDTOUT O P2 7 CTS1 P2 3 CTS0 IO P2 6 BCLK1 P2 2 BCLK0 IO A(L) A(E) P2 5 TXD1 P2 1 TXD0 IO A(L) P2 4 RXD1 P2 0 RXD0 IO A(L) DRQ3 0 I A(L) NOTES 1 READY is A(E) for the rising edge of CLKOUT S(E) for the falling edge of CLKOUT 2 Pin names in parentheses apply to the 80C188EC 80L188EC 14 80C186EC 188EC 80L186EC 188EC from the top side of the component (i e contacts facing down) Tables 7 and 8 list the pin names with package location for the 100-pin Shrink Quad Flat Pack (SQFP) component Figure 6 depicts the SQFP package as viewed from the top side of the component (i e contacts facing down) Pinout Tables 3 and 4 list the pin names with package location for the 100-pin Plastic Quad Flat Pack (PQFP) component Figure 4 depicts the PQFP package as viewed from the top side of the component (i e contacts facing down) Tables 5 and 6 list the pin names with package location for the 100-pin EIAJ Quad Flat Pack (QFP) component Figure 5 depicts the QFP package as viewed Table 3 PQFP Pin Functions with Location AD Bus Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 CAS0 (A13 CAS0) AD14 CAS1 (A14 CAS1) AD15 CAS2 (A15 CAS2) A16 S3 A17 S4 A18 S5 A19 S6 ONCE Pin 73 72 71 70 66 65 64 63 60 59 58 57 56 55 54 53 77 76 75 74 Bus Control Name ALE BHE (RFSH) S0 S1 S2 RD WR READY DEN DT R LOCK HOLD HLDA INTA Pin 52 51 78 79 80 50 49 85 47 46 48 44 45 34 Processor Control Name RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY (TEST) PEREQ (VSS) NCS (N C ) ERROR (VCC) PDTMR NMI INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Pin 8 7 10 11 6 83 81 35 84 9 82 30 31 32 33 40 41 42 43 IO Name UCS LCS P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 GCS7 GCS6 GCS5 GCS4 GCS3 GCS2 GCS1 GCS0 CTS1 BCLK1 TXD1 RXD1 CTS0 BCLK0 TXD0 RXD0 Pin 88 89 90 91 92 93 94 95 96 97 23 22 21 20 19 18 17 16 29 28 27 26 25 24 3 2 5 4 98 99 100 1 36 15 Power and Ground Name VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS Pin 13 14 38 62 67 69 86 12 15 37 39 61 68 87 DMAI1 DMAI0 TXI1 RXI1 T0IN T0OUT T1IN T1OUT DRQ0 DRQ1 DRQ2 DRQ3 WDTOUT 80C186EC 188EC 80L186EC 188EC Table 4 PQFP Pin Locations with Pin Name Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name DRQ3 T0OUT T0IN T1OUT T1IN CLKOUT RESOUT RESIN PDTMR CLKIN OSCOUT VSS VCC VCC VSS P2 0 RXD0 P2 1 TXD0 P2 2 BCLK0 P2 3 CTS0 P2 4 RXD1 P2 5 TXD1 P2 6 BCLK1 P2 7 CTS1 P3 0 RXI1 P3 1 TXI1 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name DMAI0 P3 2 DMAI1 P3 3 P3 4 P3 5 INT0 INT1 INT2 INT3 INTA NCS (N C ) WDTOUT VSS VCC VSS INT4 INT5 INT6 INT7 HOLD HLDA DT R DEN LOCK WR RD Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name BHE (RFSH) ALE AD15 (A15) AD14 (A14) AD13 (A13) AD12 (A12) AD11 (A11) AD10 (A10) AD9 (A9) AD8 (A8) VSS VCC AD7 AD6 AD5 AD4 VCC VSS VCC AD3 AD2 AD1 AD0 A19 S6 ONCE A18 S5 Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name A17 S4 A16 S3 S0 S1 S2 PEREQ (VSS) NMI TEST ERROR (VCC) READY VCC VSS UCS LCS P1 7 GCS7 P1 6 GCS6 P1 5 GCS5 P1 4 GCS4 P1 3 GCS3 P1 2 GCS2 P1 1 GCS1 P1 0 GCS0 DRQ0 DRQ1 DRQ2 16 80C186EC/188EC, 80L186EC/188EC x 272434 - 3 NOTE: This is the FPO number location (indicated by X's). Figure 4. 100-Pin Plastic Quad Flat Pack Package (PQFP) 17 80C186EC 188EC 80L186EC 188EC Table 5 QFP Pin Names with Package Location AD Bus Name AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 CAS0 (A13 CAS0) AD14 CAS1 (A14 CAS1) AD15 CAS2 (A15 CAS2) A16 S3 A17 S4 A18 S5 A19 S6 ONCE Pin 76 75 74 73 69 68 67 66 63 62 61 60 59 58 57 56 80 79 78 77 Bus Control Name ALE BHE (RFSH) S0 S1 S2 RD WR READY DEN DT R LOCK HOLD HLDA INTA Pin 55 54 81 82 83 53 52 88 50 49 51 47 48 37 Processor Control Name RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY (TEST) PEREQ (VSS) NCS (N C ) ERROR (VCC) PDTMR NMI INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Pin 11 10 13 14 9 86 84 38 87 12 85 33 34 35 36 43 44 45 46 IO Name UCS LCS P1 7 P1 6 P1 5 P1 4 P1 3 P1 2 P1 1 P1 0 P2 7 P2 6 P2 5 P2 4 P2 3 P2 2 P2 1 P2 0 P3 5 P3 4 P3 3 P3 2 P3 1 P3 0 GCS7 GCS6 GCS5 GCS4 GCS3 GCS2 GCS1 GCS0 CTS1 BCLK1 TXD1 RXD1 CTS0 BCLK0 TXD0 RXD0 Pin 91 92 93 94 95 96 97 98 99 100 26 25 24 23 22 21 20 19 32 31 30 29 28 27 6 5 8 7 1 2 3 4 39 Power and Ground Name VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS Pin 16 17 41 65 70 72 89 15 18 40 42 64 71 90 DMAI1 DMAI0 TXI1 RXI1 T0IN T0OUT T1IN T1OUT DRQ0 DRQ1 DRQ2 DRQ3 WDTOUT 18 80C186EC 188EC 80L186EC 188EC Table 6 QFP Package Location with Pin Names Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name DRQ0 DRQ1 DRQ2 DRQ3 T0OUT T0IN T1OUT T1IN CLKOUT RESOUT RESIN PDTMR CLKIN OSCOUT VSS VCC VCC VSS P2 0 RXD0 P2 1 TXD0 P2 2 BCLK0 P2 3 CTS0 P2 4 RXD1 P2 5 TXD1 P2 6 BCLK1 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name P2 7 CTS1 P3 0 RXI1 P3 1 TXI1 DMAI0 P3 2 DMAI1 P3 3 P3 4 P3 5 INT0 INT1 INT2 INT3 INTA NCS (N C ) WDTOUT VSS VCC VSS INT4 INT5 INT6 INT7 HOLD HLDA DT R DEN Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name LOCK WR RD BHE (RFSH) ALE AD15 (A15) AD14 (A14) AD13 (A13) AD12 (A12) AD11 (A11) AD10 (A10) AD9 (A9) AD8 (A8) VSS VCC AD7 AD6 AD5 AD4 VCC VSS VCC AD3 AD2 AD1 Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name AD0 A19 S6 ONCE A18 S5 A17 S4 A16 S3 S0 S1 S2 PEREQ (VSS) NMI TEST ERROR (VCC) READY VCC VSS UCS LCS P1 7 GCS7 P1 6 GCS6 P1 5 GCS5 P1 4 GCS4 P1 3 GCS3 P1 2 GCS2 P1 1 GCS1 P1 0 GCS0 19 80C186EC/188EC, 80L186EC/188EC x 272434 - 4 NOTE: This is the FPO number location (indicated by X's). Figure 5: Quad Flat Pack (EIAJ) Pinout Diagram 20 80C186EC 188EC 80L186EC 188EC Table 7 SQFP Pin Functions with Location AD Bus AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 AD8 (A8) AD9 (A9) AD10 (A10) AD11 (A11) AD12 (A12) AD13 (A13) AD14 (A14) AD15 (A15) A16 A17 A18 A19 ONCE 73 72 71 70 66 65 64 63 60 59 58 57 56 55 54 53 77 76 75 74 Bus Control ALE BHE (RFSH) S0 S1 S2 RD WR READY DT R DEN LOCK HOLD HLDA 52 51 78 79 80 50 49 85 46 47 48 44 45 Processor Control RESIN RESOUT CLKIN OSCOUT CLKOUT TEST BUSY NMI INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 INTA PEREQ (VSS) ERROR (VCC) NCS (N C ) PDTMR 8 7 10 11 6 83 82 30 31 32 33 40 41 42 43 34 81 84 35 9 UCS LCS P1 0 P1 1 P1 2 P1 3 P1 4 P1 5 P1 6 P1 7 P2 0 P2 1 P2 2 P2 3 P2 4 P2 5 P2 6 P2 7 P3 0 P3 1 P3 2 P3 3 P3 4 P3 5 GCS0 GCS1 GCS2 GCS3 GCS4 GCS5 GCS6 GCS7 RXD0 TXD0 BCLK0 CTS0 RXD1 TXD1 BCLK1 CTS1 RXI1 TXI1 DMAI0 DMAI1 IO 88 89 97 96 95 94 93 92 91 90 16 17 18 19 20 21 22 23 24 25 26 27 28 29 98 99 100 1 3 2 5 4 36 Power and Ground VCC VCC VCC VCC VCC VCC VCC VSS VSS VSS VSS VSS VSS VSS 13 14 38 62 67 69 86 12 15 37 39 61 68 87 DRQ0 DRQ1 DRQ2 DRQ3 T0IN T0OUT T1IN T1OUT WDTOUT 21 80C186EC 188EC 80L186EC 188EC Table 8 SQFP Pin Locations with Pin Names Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Name DRQ3 T0OUT T0IN T1OUT T1IN CLKOUT RESOUT RESIN PDTMR CLKIN OSCOUT VSS VCC VCC VSS P2 0 RXD0 P2 1 TXD0 P2 2 BCLK0 P2 3 CTS0 P2 4 RXD1 P2 5 TXD1 P2 6 BCLK1 P2 7 CTS1 P3 0 RXI1 P3 1 TXI1 Pin 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Name P3 2 DMAI0 P3 3 DMAI1 P3 4 P3 5 INT0 INT1 INT2 INT3 INTA NSC (N C ) WDTOUT VSS VCC VSS INT4 INT5 INT6 INT7 HOLD HLDA DT R DEN LOCK WR RD Pin 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Name BHE (RFSH) ALE AD15 (A15) AD14 (A14) AD13 (A13) AD12 (A12) AD11 (A11) AD10 (A10) AD9 (A9) AD8 (A8) VSS VCC AD7 (A7) AD6 (A6) AD5 AD4 VCC VSS VCC AD3 AD2 AD1 AD0 A19 ONCE AD18 Pin 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name A17 A16 S0 S1 S2 PEREQ (VSS) MNI TEST BUSY (TEST) ERROR (VCC) READY VCC VSS UCS LCS P1 7 GCS7 P1 6 GS6 P1 5 GCS5 P1 4 GCS4 P1 3 GCS3 P1 2 GCS2 P1 1 GCS1 P1 0 GCS0 DRQ0 DRQ1 DRQ2 22 80C186EC/188EC, 80L186EC/188EC x 272434 - 5 NOTE: This is the FPO number location (indicated by X's) Figure 6: 100-Pin Shrink Quad Flat Pack Package (SQFP) 23 80C186EC 188EC 80L186EC 188EC TA (the ambient temperature) can be calculated from iCA (thermal resistance from the case to ambient) with the following equation TA e TC b P iCA Package Thermal Specifications The 80C186EC 80L186EC is specified for operation when TC (the case temperature) is within the range of b 40 C to a 100 C TC may be measured in any environment to determine whether the processor is within the specified operating range The case temperature must be measured at the center of the top surface Typical values for iCA at various airflows are given in Table 9 P (the maximum power consumption specified in Watts) is calculated by using the maximum ICC and VCC of 5 5V Table 9 Thermal Resistance (iCA) at Various Airflows (in C Watt) Airflow in ft min (m sec) 0 (0) iCA (PQFP) iCA (QFP) iCA (SQFP) 27 0 64 5 62 0 200 (1 01) 22 0 55 5 TBD 400 (2 03) 18 0 51 0 TBD 600 (3 04) 15 0 TBD TBD 800 (4 06) 14 0 TBD TBD 1000 (5 07) 13 5 TBD TBD 24 80C186EC 188EC 80L186EC 188EC ELECTRICAL SPECIFICATIONS Absolute Maximum Ratings Storage Temperature Case Temperature Under Bias Supply Voltage with Respect to VSS Voltage on Other Pins with Respect to VSS b 65 C to a 150 C b 65 C to a 100 C b 0 5V to a 6 5V b 0 5V to VCC a 0 5V NOTICE This data sheet contains preliminary information on new products in production The specifications are subject to change without notice Verify with your local Intel Sales office that you have the latest data sheet before finalizing a design WARNING Stressing the device beyond the ``Absolute Maximum Ratings'' may cause permanent damage These are stress ratings only Operation beyond the ``Operating Conditions'' is not recommended and extended exposure beyond the ``Operating Conditions'' may affect device reliability Recommended Connections Power and ground connections must be made to multiple VCC and VSS pins Every 80C186EC-based circuit board should include separate power (VCC) and ground (VSS) planes Every VCC pin must be connected to the power plane and every VSS pin must be connected to the ground plane Liberal decoupling capacitance should be placed near the processor The processor can cause transient power surges when its output buffers transition particularly when connected to large capacitive loads Low inductance capacitors and interconnects are recommended for best high frequency electrical performance Inductance is reduced by placing the decoupling capacitors as close as possible to the processor VCC and VSS package pins Always connect any unused input to an appropriate signal level In particular unused interrupt inputs (NMI INT0 7) should be connected to VSS through a pull-down resistor Leave any unused output pin unconnected 25 80C186EC 188EC 80L186EC 188EC DC SPECIFICATIONS (80C186EC 80C188EC) Symbol VCC VIL VIH VOL VOH VHYR ILI Parameter Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Hysteresis on RESIN Input Leakage Current for Pins AD15 0 (AD7 0 A15 8) READY HOLD RESIN CLKIN TEST BUSY NMI INT7 0 T0IN T1IN P2 7-P2 0 P3 5-P3 0 DRQ3 0 PEREQ ERROR Input Leakage for Pins with Pullups Active During Reset A19 16 LOCK Output Leakage for Floated Output Pins Supply Current Cold (in RESET) 80C186EC25 80C186EC20 80C186EC13 Supply Current in Idle Mode 80C186EC25 80C186EC20 80C186EC13 Supply Current in Powerdown Mode 80C186EC25 80C186EC20 80C186EC13 Input Pin Capacitance Output Pin Capacitance 0 0 b 0 275 Min 45 b0 5 Max 55 0 3 VCC VCC a 0 5 0 45 Units V V V V V V Notes 0 7 VCC VCC b 0 5 05 IOL e 3 mA (Min) IOH e b 2 mA (Min) 0 s VIN s VCC g15 mA ILIU b5 mA VIN e 0 7 VCC (Note 1) 0 45 s VOUT s VCC (Note 2) (Notes 3 7) (Note 3) (Note 3) (Notes 4 7) (Note 4) (Note 4) (Notes 5 7) (Note 5) (Note 5) TF e 1 MHz TF e 1 MHz (Note 6) ILO ICC g15 mA 125 100 70 92 76 50 100 100 100 15 15 mA mA mA mA mA mA mA mA mA pF pF IID IPD CIN COUT NOTES 1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified (on any of these pins) may invoke a factory test mode 2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD 3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 6 Output Capacitance is the capacitive load of a floating output pin 7 Operating conditions for 25 MHz is 0 C to a 70 C VCC e 5 0 g10% 26 80C186EC 188EC 80L186EC 188EC DC SPECIFICATIONS (80L186EC13 80L188EC13) Symbol VCC VIL VIH VOL VOH VHYR ILI Parameter Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Hysteresis on RESIN Input Leakage Current for Pins AD15 0 (AD7 0 A15 8) READY HOLD RESIN CLKIN TEST BUSY NMI INT7 0 T0IN T1IN P2 7-P2 0 P3 5-P3 0 DRQ3 0 PEREQ ERROR Input Leakage for Pins with Pullups Active During Reset A19 16 LOCK Output Leakage for Floated Output Pins Supply Current Cold (in RESET) 80L186EC-13 Supply Current in Idle Mode 80L186EC-13 Supply Current in Powerdown Mode 80L186EC-13 Input Pin Capacitance Output Pin Capacitance 0 0 b 0 275 Min 27 b0 5 Max 55 0 3 VCC VCC a 0 5 0 45 Units V V V V V V Notes 0 7 VCC VCC b 0 5 05 IOL e 3 mA (Min) IOH e b 2 mA (Min) 0 s VIN s VCC g15 mA ILIU b5 mA VIN e 0 7 VCC (Note 1) 0 45 s VOUT s VCC (Note 2) (Note 3) ILO ICC IID IPD CIN COUT g15 mA 36 24 30 15 15 mA (Note 4) mA (Note 5) mA pF pF TF e 1 MHz TF e 1 MHz (Note 6) NOTES 1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified (on any of these pins) may invoke a factory test mode 2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD 3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 6 Output Capacitance is the capacitive load of a floating output pin 27 80C186EC 188EC 80L186EC 188EC DC SPECIFICATIONS (80L186EC16 80L188EC16) Symbol VCC VIL VIH VOL VOH VHYR ILI Parameter Supply Voltage Input Low Voltage Input High Voltage Output Low Voltage Output High Voltage Input Hysteresis on RESIN Input Leakage Current for Pins AD15 0 (AD7 0 A15 8) READY HOLD RESIN CLKIN TEST BUSY NMI INT7 0 T0IN T1IN P2 7-P2 0 P3 5-P3 0 DRQ3 0 PEREQ ERROR Input Leakage for Pins with Pullups Active During Reset A19 16 LOCK Output Leakage for Floated Output Pins Supply Current Cold (in RESET) 80L186EC-16 Supply Current in Idle Mode 80L186EC-16 Supply Current in Powerdown Mode 80L186EC-16 Input Pin Capacitance Output Pin Capacitance 0 0 b 0 275 (Operating Temperature 0 C to 70 C) Max 55 0 3 VCC Units V V V V V V g15 Min 30 b0 5 Notes 0 7 VCC VCC b 0 5 05 VCC a 0 5 0 45 IOL e 3 mA (Min) IOH e b 2 mA (Min) 0 s VIN s VCC mA ILIU b5 mA VIN e 0 7 VCC (Note 1) 0 45 s VOUT s VCC (Note 2) (Note 3) ILO ICC IID IPD CIN COUT g15 mA 45 35 50 15 15 mA (Note 4) mA (Note 5) mA pF pF TF e 1 MHz TF e 1 MHz (Note 6) NOTES 1 These pins have an internal pull-up device that is active while RESIN is low and ONCE Mode is not active Sourcing more current than specified (on any of these pins) may invoke a factory test mode 2 Tested by outputs being floated by invoking ONCE Mode or by asserting HOLD 3 Measured with the device in RESET and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 4 Measured with the device in HALT (IDLE Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 5 Measured with the device in HALT (Powerdown Mode active) and at worst case frequency VCC and temperature with ALL outputs loaded as specified in AC Test Conditions and all floating outputs driven to VCC or GND 6 Output Capacitance is the capacitive load of a floating output pin 28 80C186EC 188EC 80L186EC 188EC ICC versus Frequency and Voltage The ICC consumed by the processor is composed of two components 1 IPD The quiescent current that represents internal device leakage Measured with all inputs at either VCC or ground and no clock applied 2 ICCS The switching current used to charge and discharge internal parasitic capacitance when changing logic levels ICCS is related to both the frequency of operation and the device supply voltage (VCC) ICCS is given by the formula Power e V I e V2 CDEV f f PDTMR Pin Delay Calculation The PDTMR pin provides a delay between the assertion of NMI and the enabling of the internal clocks when exiting Powerdown Mode A delay is required only when using the on chip oscillator to allow the crystal or resonator circuit to stabilize NOTE The PDTMR pin function does not apply when RESIN is asserted (i e a device reset while in Powerdown is similar to a cold reset and RESIN must remain active until after the oscillator has stabilized To calculate the value of capacitor to use to provide a desired delay use the equation 440 c t e CPD (5V 25 C) ICCS e V CDEV Where V e Supply Voltage (VCC) CDEV e Device Capacitance f e Operating Frequency Measuring CPD on a device like the 80C186EC would be difficult Instead CPD is calculated using the above formula with ICC values measured at known VCC and frequency Using the CPD value the user can calculate ICC at any voltage and frequency within the specified operating range Example Calculate typical ICC at 14 MHz 5 2V VCC ICC e IPD a ICCS e 0 1 mA a 5 2V e 56 2 mA Where t e desired delay in seconds CPD e capacitive load on PDTMR in microfarads Example For a delay of 300 ms a capacitor value of CPD e 440 c (300 c 10b6 e 0 132 mF is required Round up to a standard (available) capacitor value NOTE The above equation applies to delay time longer than 10 ms and will compute the TYPICAL capacitance needed to achieve the desired delay A delay variance of a 50% to b 25% can occur due to temperature voltage and device process extremes In general higher VCC and or lower temperatures will decrease delay time while lower VCC and or higher temperature will increase delay time Max 1 37 0 96 Units mA V MHz mA V MHz Notes 12 12 0 77 14 MHz Parameter CPD CPD (Idle Mode) Typical 0 77 0 55 NOTES 1 Maximum CPD is measured at b40 C with all outputs loaded as specified in the AC test conditions and the device in reset (or Idle Mode) Due to tester limitations CLKOUT and OSCOUT also have 50 pF loads that increase ICC by V C F 2 Typical CPD is calculated at 25 C assuming no loads on CLKOUT or OSCOUT and the device in reset (or Idle Mode) 29 80C186EC 188EC 80L186EC 188EC AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCLOV1 TCLOV2 TCHOF TCLOF CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time 0 20 8 8 1 1 50 % % % 10 10 MHz ns ns ns ns ns 1 1 12 12 13 13 80C186EC25 Parameter 25 MHz Min Max Units Notes OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time 0 (T 2) b 5 (T 2) b 5 1 1 17 2 TC (T 2) a 5 (T 2) a 5 6 6 ns ns ns ns ns ns 14 1 1 1 15 15 OUTPUT DELAYS ALE S2 0 DEN DT R BHE (RFSH) LOCK A19 16 GCS0 7 LCS UCS NCS RD WR BHE (RFSH) DEN LOCK RESOUT HLDA T0OUT T1OUT A19 16 RD WR GCS7 0 LCS UCS AD15 0 (AD7 0 A15 8) NCS INTA1 0 S2 0 RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (AD7 0 A15 8) 3 3 3 3 0 0 17 20 17 20 20 20 ns ns ns ns ns ns 1467 1468 146 146 1 1 30 80C186EC 188EC 80L186EC 188EC AC SPECIFICATIONS AC Characteristics Symbol SYNCHRONOUS INPUTS TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 P2 6 P2 7 TEST NMI INT4 0 BCLK1 0 T1 0IN READY CTS1 0 AD15 0 (AD7 0) READY READY AD15 0 (AD7 0) HOLD PEREQ ERROR HOLD PEREQ ERROR 10 3 10 3 10 3 ns ns ns ns ns ns 19 19 1 10 1 10 19 19 80C186EC25 (Continued) Parameter 25 MHz Min Max Units Notes NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 13 for capacitive derating information 5 Specified for a 50 pF load see Figure 14 for rise and fall times outside 50 pF 6 See Figure 14 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 31 80C186EC 188EC 80L186EC 188EC AC SPECIFICATIONS AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time 0 25 10 10 1 1 0 80C186EC-20 80C186EC-13 Min Max 40 % % % 10 10 Min 0 38 5 12 12 1 1 Max 26 % % % 10 10 Unit Notes MHz ns ns ns ns ns ns ns ns ns ns ns 1 1 12 12 13 13 14 1 1 1 15 15 20 MHz 13 MHz Parameter OUTPUT CLOCK 17 0 23 2 TC 2 TC (T 2) b 5 (T 2) a 5 (T 2) b 5 (T 2) a 5 (T 2) b 5 (T 2) a 5 (T 2) b 5 (T 2) a 5 1 6 1 6 1 6 1 6 3 3 3 3 0 0 10 3 10 3 10 3 20 23 20 23 25 25 3 3 3 3 0 0 10 3 10 3 10 3 25 30 25 30 30 30 OUTPUT DELAYS TCHOV1 ALE S2 0 DEN DT R BHE (RFSH) LOCK A19 16 TCHOV2 GCS7 0 LCS UCS RD WR NCS WDTOUT TCLOV1 BHE (RFSH) DEN LOCK RESOUT HLDA T0OUT T1OUT TCLOV2 RD WR GSC7 0 LCS UCS AD15 0 (AD7 0 A15 8) NCS INTA S2 0 A19 16 TCHOF TCLOF TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (AD7 0 A15 8) TEST NMI T1IN T0IN READY CTS1 0 BCLK1 0 P3 4 P3 5 TEST NMI T1IN T0IN READY CTS1 0 BCLK1 0 P3 4 P3 5 AD15 0 (AD7 0) READY AD15 0 (AD7 0) READY HOLD RESIN PEREQ ERROR DRQ3 0 HOLD RESIN REREQ ERROR DRQ3 0 ns 1 4 6 7 ns 1 4 6 8 ns ns ns ns ns ns ns ns ns ns 146 146 1 1 19 19 1 10 1 10 19 19 INPUT REQUIREMENTS NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 14 for capacitive derating information 5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF 6 See Figure 15 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation 32 80C186EC 188EC 80L186EC 188EC AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCHOV3 TCLOV1 TCLOV2 TCLOV3 TCLOV4 TCHOF TCLOF TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH 80L186EC13 Parameter Min 13 MHz 0 38 5 15 15 1 1 26 % % % 10 10 MHz ns ns ns ns ns 1 1 12 12 13 13 Max Unit Notes CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time 0 (T 2) b 5 (T 2) b 5 1 1 20 2 TC (T 2) a 5 (T 2) a 5 10 10 ns ns ns ns ns ns 14 1 1 1 15 15 OUTPUT DELAYS S2 0 DT R BHE LOCK LCS UCS DEN A19 16 RD WR NCS WDTOUT ALE GCS7 0 LOCK RESOUT HLDA T0OUT T1OUT RD WR AD15 0 (AD7 0 A15 8) BHE (RFSH) NCS INTA DEN GSC7 0 LCS UCS S2 0 A19 16 RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (AD7 0 A15 8) 3 3 3 3 3 3 3 0 0 28 32 34 28 32 34 37 30 35 ns ns ns ns ns ns ns ns ns 1467 1468 146 146 146 146 146 1 1 INPUT REQUIREMENTS TEST NMI T1IN T0IN READY CTS1 0 BCLK1 0 P3 4 P3 5 TEST NMI T1IN T0IN READY CTS1 0 BCLK1 0 P3 4 P3 5 AD15 0 (AD7 0) READY AD15 0 (AD7 0) READY HOLD RESIN PEREQ ERROR DRQ3 0 HOLD RESIN REREQ ERROR DRQ3 0 20 3 20 3 20 3 ns ns ns ns ns ns 19 19 1 10 1 10 19 19 NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 14 for capacitive derating information 5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF 33 80C186EC 188EC 80L186EC 188EC AC Characteristics 80L186EC13 (Continued) NOTES 6 See Figure 15 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation AC Characteristics Symbol INPUT CLOCK TF TC TCH TCL TCR TCF TCD T TPH TPL TPR TPF TCHOV1 TCHOV2 TCHOV3 TCLOV1 TCLOV2 TCLOV3 TCLOV4 TCHOF TCLOF TCHIS TCHIH TCLIS TCLIH TCLIS TCLIH 34 80L186EC16 (Operating Temperature 0 C to 70 C) Parameter Min 16 MHz 0 31 25 13 13 1 1 32 % % % 10 10 MHz ns ns ns ns ns 1 1 12 12 13 13 Max Unit Notes CLKIN Frequency CLKIN Period CLKIN High Time CLKIN Low Time CLKIN Rise Time CLKIN Fall Time OUTPUT CLOCK CLKIN to CLKOUT Delay CLKOUT Period CLKOUT High Time CLKOUT Low Time CLKOUT Rise Time CLKOUT Fall Time 0 (T 2) b 5 (T 2) b 5 1 1 20 2 TC (T 2) a 5 (T 2) a 5 9 9 ns ns ns ns ns ns 14 1 1 1 15 15 OUTPUT DELAYS S2 0 DT R BHE LOCK LCS UCS DEN A19 16 RD WR NCS WDTOUT ALE GCS7 0 LOCK RESOUT HLDA T0OUT T1OUT RD WR AD15 0 (AD7 0 A15 8) BHE (RFSH) NCS INTA DEN GSC7 0 LCS UCS S2 0 A19 16 RD WR BHE (RFSH) DT R LOCK S2 0 A19 16 DEN AD15 0 (AD7 0 A15 8) 3 3 3 3 3 3 3 0 0 25 30 32 25 30 32 34 28 32 ns ns ns ns ns ns ns ns ns 1467 1468 146 146 146 146 146 1 1 INPUT REQUIREMENTS TEST NMI T1IN T0IN READY CTS1 0 BCLK1 0 P3 4 P3 5 TEST NMI T1IN T0IN READY CTS1 0 BCLK1 0 P3 4 P3 5 AD15 0 (AD7 0) READY AD15 0 (AD7 0) READY HOLD RESIN PEREQ ERROR DRQ3 0 HOLD RESIN PEREQ ERROR DRQ3 0 15 3 15 3 15 3 ns ns ns ns ns ns 19 19 1 10 1 10 19 19 80C186EC 188EC 80L186EC 188EC AC Characteristics 80L186EC16 (Continued) NOTES 1 See AC Timing Waveforms for waveforms and definition 2 Measure at VIH for high time VIL for low time 3 Only required to guarantee ICC Maximum limits are bounded by TC TCH and TCL 4 Specified for a 50 pF load see Figure 14 for capacitive derating information 5 Specified for a 50 pF load see Figure 15 for rise and fall times outside 50 pF 6 See Figure 15 for rise and fall times 7 TCHOV1 applies to BHE (RFSH) LOCK and A19 16 only after a HOLD release 8 TCHOV2 applies to RD and WR only after a HOLD release 9 Setup and Hold are required to guarantee recognition 10 Setup and Hold are required for proper operation Relative Timings (80C186EC-25 20 13 80L186EC-16 13) Symbol RELATIVE TIMINGS TLHLL TAVLL TPLLL TLLAX TLLWL TLLRL TWHLH TAFRL TRLRH TWLWH TRHAX TWHDX TWHPH TRHPH TPHPL TOVRH TRHOX TIHIL TILIH TCVIL TILCX TIRES TIRLH TIRHIF ALE Active Pulse Width AD Valid Setup before ALE Falls Chip Select Valid before ALE Falls AD Hold after ALE Falls ALE Falling to WR Falling ALE Falling to RD Falling WR Rising to Next ALE Rising AD Float to RD Falling RD Active Pulse Width WR Active Pulse Width RD Rising to Next Address Active Output Data Hold after WR Rising WR Rise to Chip Select Rise RD Rise to Chip Select Rise Chip Select Inactive to Next Chip Select Active ONCE Active Setup to RESIN Rising ONCE Hold after RESIN Rise INTA High to Next INTA Low during INTA Cycle INTA Active Pulse Width CAS2 0 Setup before 2nd INTA Pulse Low CAS2 0 Hold after 2nd INTA Pulse Low Interrupt Resolution Time IR Low Time to Reset Edge Detector IR Hold Time after 1st INTA Falling 50 25 T b 15 T b 10 T b 10 T b 10 T b 15 T b 15 T b 10 0 2T b 5 2T b 5 T b 15 T b 15 T b 10 T b 10 T b 10 T T 4T b 5 2T b 5 8T 4T 150 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 45 4 24 24 24 3 1 1 1 2 2 1 1 1 1 Parameter Min Max Unit Notes 35 80C186EC 188EC 80L186EC 188EC Relative Timings (80C186EC-25 20 13 80L186EC-16 13) NOTES 1 Assumes equal loading on both pins 2 Can be extended using wait states 3 Interrupt resolution time is the delay between an unmasked interrupt request going active and the interrupt output of the 8259A module going active This is not directly measureable by the user For interrupt pin INT7 the delay from an active signal to an active input to the CPU would actually be twice the TIRES value since the signal must pass through two 8259A modules 4 See INTA Cycle Waveforms for definition 5 To guarantee interrupt is not spurious Serial Port Mode 0 Timings (80C186EC-25 20 13 80L186EC-16 13) Symbol RELATIVE TIMINGS TXLXL TXLXH TXLXH TXHXL TXHXL TQVXH TQVXH TXHQX TXHQX TXHQZ TDVXH TXHDX TXD Clock Period TXD Clock Low to Clock High (N l 1) TXD Clock Low to Clock High (N e 1) TXD Clock High to Clock Low (N l 1) TXD Clock High to Clock Low (N e 1) RXD Output Data Setup to TXD Clock High (N l 1) RXD Output Data Setup to TXD Clock High (N e 1) RXD Output Data Hold after TXD Clock High (N l 1) RXD Output Data Hold after TXD Clock High (N e 1) RXD Output Data Float after Last TXD Clock High RXD Input Data Setup to TXD Clock High RXD Input Data Setup after TXD Clock High T a 20 0 T (n a 1) 2T b 35 T b 35 (n b 1) T b 35 T b 35 (n b 1)T b 35 T b 35 2T b 35 T b 35 T a 20 2T a 35 T a 35 (n b 1) T a 35 T a 35 ns ns ns ns ns ns ns ns ns ns ns ns 12 1 1 12 1 12 1 1 1 1 1 1 Parameter Min Max Unit Notes NOTES 1 See Figure 13 for Waveforms 2 n is the value in the BxCMP register ignoring the ICLK bit 36 80C186EC 188EC 80L186EC 188EC AC TEST CONDITIONS The AC specifications are tested with the 50 pF load shown in Figure 7 See the Derating Curves section to see how timings vary with load capacitance Specifications are measured at the VCC 2 crossing point unless otherwise specified See AC Timing Waveforms for AC specification definitions test pins and illustrations CL e 50 pF for all signals 272434 - 6 Figure 7 AC Test Load AC TIMING WAVEFORMS 272434 - 7 Figure 8 Input and Output Clock Waveforms 37 80C186EC 188EC 80L186EC 188EC 272434 - 8 Figure 9 Output Delay and Float Waveforms 272434 - 9 Figure 10 Input Setup and Hold 272434 - 10 Figure 11 Relative Interrupt Signal Timings 38 80C186EC 188EC 80L186EC 188EC 272434 - 11 Figure 12 Relative Signal Waveform 272434 - 12 Figure 13 Serial Port Mode 0 Waveform 39 80C186EC 188EC 80L186EC 188EC DERATING CURVES 272434 - 13 Figure 14 Typical Output Delay Variations versus Load Capacitance 272434 - 14 Figure 15 Typical Rise and Fall Variations versus Load Capacitance RESET The processor will perform a reset operation any time the RESIN pin is active The RESIN pin is synchronized before it is presented internally which means that the clock must be operating before a reset can take effect From a power-on state RESIN must be held active (low) in order to guarantee correct initialization of the processor Failure to provide RESIN while the device is powering up will result in unspecified operation of the device Figure 16 shows the correct reset sequence when first applying power to the processor An external clock connected to CLKIN must not exceed the VCC threshold being applied to the processor This is normally not a problem if the clock driver is supplied with the same VCC that supplies the processor When attaching a crystal to the device RESIN must remain active until both VCC and CLKOUT are stable (the length of time is application specific and depends on the startup characteristics of the crystal circuit) The RESIN pin is designed to operate cor40 rectly using a RC reset circuit but the designer must ensure that the ramp time for VCC is not so long that RESIN is never sampled at a logic low level when VCC reaches minimum operating conditions Figure 17 shows the timing sequence when RESIN is applied after VCC is stable and the device has been operating Note that a reset will terminate all activity and return the processor to a known operating state Any bus operation that is in progress at the time RESIN is asserted will terminate immediately (note that most control signals will be driven to their inactive state first before floating) While RESIN is active bus signals LOCK A19 S16 ONCE and A18 16 are configured as inputs and weakly held high by internal pullup transistors Only A19 ONCE can be overdriven to a low and is used to enable the ONCE Mode Forcing LOCK or A18 16 low at any time while RESIN is low is prohibited and will cause unspecified device operation Figure 16 Cold RESET Waveforms 272434- 15 NOTE CLKOUT synchronization occurs on the rising edge of RESIN If RESIN is sampled high while CLKOUT is high (solid line) then CLKOUT will remain low for two CLKIN periods If RESIN is sampled high while CLKOUT is low (dashed line) then CLKOUT will not be affected 80C186EC 188EC 80L186EC 188EC Pin names in parentheses apply to 80C188EC 80L188EC 41 42 272434- 16 80C186EC 188EC 80L186EC 188EC Figure 17 Warm RESET Waveforms NOTE CLKOUT synchronization occurs on the rising edge of RESIN If RESIN is sampled high while CLKOUT is high (solid line) then CLKOUT will remain low for two CLKIN periods If RESIN is sampled high while CLKOUT is low (dashed line) then CLKOUT will not be affected Pin names in parentheses apply to 80C188EC 80L188EC 80C186EC 188EC 80L186EC 188EC bus signals to CLKOUT These figures along with the information present in AC Specifications allow the user to determine all the critical timing analysis needed for a given application BUS CYCLE WAVEFORMS Figures 18 through 24 present the various bus cycles that are generated by the processor What is shown in the figure is the relationship of the various 272434 - 17 Pin names in parentheses apply to 80C188EC 80L188EC Figure 18 Memory Read I O Read Instruction Fetch and Refresh Waveforms 43 80C186EC 188EC 80L186EC 188EC 272434 - 18 Pin names in parentheses apply to 80C188EC 80L188EC Figure 19 Memory Write and I O Write Cycle Waveforms 44 80C186EC 188EC 80L186EC 188EC 272434 - 19 NOTES 1 Address information is invalid If previous bus cycle was a read then the AD15 0 (AD7 0) lines will float during T1 Otherwise the AD15 0 (AD7 0) lines will continue to drive during T1 (data is invalid) All other control lines are in their inactive state 2 All address lines drive zeros while in Powerdown or Idle Mode Pin names in parentheses apply to 80C188EC 80L188EC Figure 20 Halt Cycle Waveforms 45 80C186EC 188EC 80L186EC 188EC 272434 - 20 Pin names in parentheses apply to 80C188EC 80L188EC Figure 21 Interrupt Acknowledge Cycle Waveforms 46 80C186EC 188EC 80L186EC 188EC 272434 - 21 Pin names in parentheses apply to 80C188EC 80L188EC Figure 22 HOLD HLDA Cycle Waveforms 47 80C186EC 188EC 80L186EC 188EC 272434 - 22 Pin names in parentheses apply to 80C188EC 80L188EC Figure 23 Refresh during HLDA Waveforms 48 80C186EC 188EC 80L186EC 188EC 272434 - 23 NOTES 1 READY must be low by either edge to cause a wait state 2 Lighter lines indicate READ cycles darker lines indicate WRITE cycles Pin names in parentheses apply to 80C188EC 80L188EC Figure 24 READY Cycle Waveforms 49 80C186EC 188EC 80L186EC 188EC All instructions which involve memory accesses can require one or two additional clocks above the minimum timings shown due to the asynchronous handshake between the bus interface unit (BIU) and execution unit With a 16-bit BIU the 80C186EC has sufficient bus performance to ensure that an adequate number of prefetched bytes will reside in the queue (6 bytes) most of the time Therefore actual program execution time will not be substantially greater than that derived from adding the instruction timings shown The 80C188EC 8-bit BIU is limited in its performance relative to the execution unit A sufficient number of prefetched bytes may not reside in the prefetch queue (4 bytes) much of the time Therefore actual program execution time will be substantially greater than that derived from adding the instruction timings shown 80C186EC 80C188EC EXECUTION TIMINGS A determination of program execution timing must consider the bus cycles necessary to prefetch instructions as well as the number of execution unit cycles necessary to execute instructions The following instruction timings represent the minimum execution time in clock cycles for each instruction The timings given are based on the following assumptions The opcode along with any data or displacement required for execution of a particular instruction has been prefetched and resides in the queue at the time it is needed No wait states or bus HOLDs occur All word-data is located on even-address boundaries (80C186EC only) All jumps and calls include the time required to fetch the opcode of the next instruction at the destination address 50 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY Function DATA TRANSFER MOV e Move Register to Register Memory Register memory to register Immediate to register memory Immediate to register Memory to accumulator Accumulator to memory Register memory to segment register Segment register to register memory PUSH e Push Memory Register Segment register Immediate PUSHA e Push All POP e Pop Memory Register Segment register POPA e Pop All XCHG e Exchange Register memory with register Register with accumulator IN e Input from Fixed port Variable port OUT e Output to Fixed port Variable port XLAT e Translate byte to AL LEA e Load EA to register LDS e Load pointer to DS LES e Load pointer to ES LAHF e Load AH with flags SAHF e Store AH into flags PUSHF e Push flags POPF e Pop flags 1110011w 1110111w 11010111 10001101 11000101 11000100 10011111 10011110 10011100 10011101 mod reg r m mod reg r m mod reg r m (mod i 11) (mod i 11) port 9 7 11 6 18 18 2 3 9 8 9 7 15 6 26 26 2 3 13 12 1110010w 1110110w port 10 8 10 8 1000011w 1 0 0 1 0 reg mod reg r m 4 17 3 4 17 3 10001111 0 1 0 1 1 reg 0 0 0 reg 1 1 1 01100001 (reg i 01) mod 0 0 0 r m 20 10 8 51 24 14 12 83 11111111 0 1 0 1 0 reg 0 0 0 reg 1 1 0 011010s0 01100000 data data if s e 0 mod 1 1 0 r m 16 10 9 10 36 20 14 13 14 68 1000100w 1000101w 1100011w 1 0 1 1 w reg 1010000w 1010001w 10001110 10001100 mod reg r m mod reg r m mod 000 r m data addr-low addr-low mod 0 reg r m mod 0 reg r m data data if w e 1 addr-high addr-high data if w e 1 2 12 29 12 13 34 8 9 29 2 11 2 12 29 12 13 34 8 9 2 13 2 15 8 16-bit 8 16-bit Format 80C186EC Clock Cycles 80C188EC Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers 51 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) Function DATA TRANSFER (Continued) SEGMENT e Segment Override CS SS DS ES ARITHMETIC ADD e Add Reg memory with register to either Immediate to register memory Immediate to accumulator ADC e Add with carry Reg memory with register to either Immediate to register memory Immediate to accumulator INC e Increment Register memory Register SUB e Subtract Reg memory and register to either Immediate from register memory Immediate from accumulator SBB e Subtract with borrow Reg memory and register to either Immediate from register memory Immediate from accumulator DEC e Decrement Register memory Register CMP e Compare Register memory with register Register with register memory Immediate with register memory Immediate with accumulator NEG e Change sign register memory AAA e ASCII adjust for add DAA e Decimal adjust for add AAS e ASCII adjust for subtract DAS e Decimal adjust for subtract MUL e Multiply (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word 0011101w 0011100w 100000sw 0011110w 1111011w 00110111 00100111 00111111 00101111 1111011w mod 100 r m 26-28 35-37 32-34 41-43 26-28 35-37 32-34 41-43 mod reg r m mod reg r m mod 1 1 1 r m data mod 0 1 1 r m data data if w e 1 data if s w e 01 3 10 3 10 3 10 34 3 10 8 4 7 4 3 10 3 10 3 10 34 3 10 8 4 7 4 8 16-bit 1111111w 0 1 0 0 1 reg mod 0 0 1 r m 3 15 3 3 15 3 000110dw 100000sw 0001110w mod reg r m mod 0 1 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 001010dw 100000sw 0010110w mod reg r m mod 1 0 1 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 1111111w 0 1 0 0 0 reg mod 0 0 0 r m 3 15 3 3 15 3 000100dw 100000sw 0001010w mod reg r m mod 0 1 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 000000dw 100000sw 0000010w mod reg r m mod 0 0 0 r m data data data if w e 1 data if s w e 01 3 10 4 16 34 3 10 4 16 34 8 16-bit 00101110 00110110 00111110 00100110 2 2 2 2 2 2 2 2 Format 80C186EC Clock Cycles 80C188EC Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers 52 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) Function ARITHMETIC (Continued) IMUL e Integer multiply (signed) Register-Byte Register-Word Memory-Byte Memory-Word IMUL e Integer Immediate multiply (signed) DIV e Divide (unsigned) Register-Byte Register-Word Memory-Byte Memory-Word IDIV e Integer divide (signed) Register-Byte Register-Word Memory-Byte Memory-Word AAM e ASCII adjust for multiply AAD e ASCII adjust for divide CBW e Convert byte to word CWD e Convert word to double word LOGIC Shift Rotate Instructions Register Memory by 1 Register Memory by CL Register Memory by Count 1101000w 1101001w 1100000w mod TTT r m mod TTT r m mod TTT r m TTT Instruction 000 ROL 001 ROR 010 RCL 011 RCR 1 0 0 SHL SAL 101 SHR 111 SAR AND e And Reg memory and register to either Immediate to register memory Immediate to accumulator TEST e And function to flags no result Register memory and register Immediate data and register memory Immediate data and accumulator OR e Or Reg memory and register to either Immediate to register memory Immediate to accumulator 000010dw 1000000w 0000110w mod reg r m mod 0 0 1 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit 1000010w 1111011w 1010100w mod reg r m mod 0 0 0 r m data data data if w e 1 data if w e 1 3 10 4 10 34 3 10 4 10 34 8 16-bit 001000dw 1000000w 0010010w mod reg r m mod 1 0 0 r m data data data if w e 1 data if w e 1 3 10 4 16 34 3 10 4 16 34 8 16-bit count 2 15 2 15 11010100 11010101 10011000 10011001 00001010 00001010 1111011w mod 1 1 1 r m 44-52 53-61 50-58 59-67 19 15 2 4 44-52 53-61 50-58 59-67 19 15 2 4 011010s1 mod reg r m data data if s e 0 1111011w mod 1 0 1 r m 25-28 34-37 31-34 40-43 22-25 29-32 25-28 34-37 32-34 40-43 22-25 29-32 Format 80C186EC Clock Cycles 80C188EC Clock Cycles Comments 1111011w mod 1 1 0 r m 29 38 35 44 29 38 35 44 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n 5 a n 17 a n Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers 53 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) Function LOGIC (Continued) XOR e Exclusive or Reg memory and register to either Immediate to register memory Immediate to accumulator NOT e Invert register memory STRING MANIPULATION MOVS e Move byte word CMPS e Compare byte word SCAS e Scan byte word LODS e Load byte wd to AL AX STOS e Store byte wd from AL AX INS e Input byte wd from DX port OUTS e Output byte wd to DX port 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 14 22 15 12 10 14 14 14 22 15 12 10 14 14 001100dw 1000000w 0011010w 1111011w mod reg r m mod 1 1 0 r m data mod 0 1 0 r m data data if w e 1 data if w e 1 3 10 4 16 34 3 10 3 10 4 16 34 3 10 8 16-bit Format 80C186EC Clock Cycles 80C188EC Clock Cycles Comments Repeated by count in CX (REP REPE REPZ REPNE REPNZ) MOVS e Move string CMPS e Compare string SCAS e Scan string LODS e Load string STOS e Store string INS e Input string OUTS e Output string CONTROL TRANSFER CALL e Call Direct within segment Register memory indirect within segment Direct intersegment 11101000 11111111 disp-low mod 0 1 0 r m disp-high 15 13 19 19 17 27 11110010 1111001z 1111001z 11110010 11110010 11110010 11110010 1010010w 1010011w 1010111w 1010110w 1010101w 0110110w 0110111w 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 8 a 8n 5 a 22n 5 a 15n 6 a 11n 6 a 9n 8 a 8n 8 a 8n 10011010 segment offset segment selector 23 31 Indirect intersegment JMP e Unconditional jump Short long Direct within segment Register memory indirect within segment Direct intersegment 11111111 mod 0 1 1 r m (mod i 11) 38 54 11101011 11101001 11111111 disp-low disp-low mod 1 0 0 r m disp-high 14 14 11 17 14 14 11 21 11101010 segment offset segment selector 14 14 Indirect intersegment 11111111 mod 1 0 1 r m (mod i 11) 26 34 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers 54 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) Function CONTROL TRANSFER (Continued) RET e Return from CALL Within segment Within seg adding immed to SP Intersegment Intersegment adding immediate to SP JE JZ e Jump on equal zero JL JNGE e Jump on less not greater or equal JLE JNG e Jump on less or equal not greater JB JNAE e Jump on below not above or equal JBE JNA e Jump on below or equal not above JP JPE e Jump on parity parity even JO e Jump on overflow JS e Jump on sign JNE JNZ e Jump on not equal not zero JNL JGE e Jump on not less greater or equal JNLE JG e Jump on not less or equal greater JNB JAE e Jump on not below above or equal JNBE JA e Jump on not below or equal above JNP JPO e Jump on not par par odd JNO e Jump on not overflow JNS e Jump on not sign JCXZ e Jump on CX zero LOOP e Loop CX times LOOPZ LOOPE e Loop while zero equal LOOPNZ LOOPNE e Loop while not zero equal ENTER e Enter Procedure Le0 Le1 Ll1 LEAVE e Leave Procedure INT e Interrupt Type specified Type 3 INTO e Interrupt on overflow 11001101 11001100 11001110 type 47 45 48 4 47 45 48 4 if INT taken if INT not taken 11001001 11000011 11000010 11001011 11001010 01110100 01111100 01111110 01110010 01110110 01111010 01110 000 01111000 01110101 01111101 01111111 01110011 01110111 01111011 01110001 01111001 11100011 11100010 11100001 11100000 11001000 data-low disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp disp data-low data-high L 15 19 25 29 22 a 16(n b 1) 26 a 20(n b 1) 8 8 data-high data-low data-high 16 18 22 25 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 20 22 30 33 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 4 13 5 15 6 16 6 16 6 16 LOOP not taken LOOP taken JMP not taken JMP taken Format 80C186EC Clock Cycles 80C188EC Clock Cycles Comments IRET e Interrupt return BOUND e Detect value out of range 11001111 01100010 mod reg r m 28 33-35 28 33-35 Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers 55 80C186EC 188EC 80L186EC 188EC INSTRUCTION SET SUMMARY (Continued) Function PROCESSOR CONTROL CLC e Clear carry CMC e Complement carry STC e Set carry CLD e Clear direction STD e Set direction CLI e Clear interrupt STI e Set interrupt HLT e Halt WAIT e Wait LOCK e Bus lock prefix NOP e No Operation 11111000 11110101 11111001 11111100 11111101 11111010 11111011 11110100 10011011 11110000 10010000 (TTT LLL are opcode to processor extension) 2 2 2 2 2 2 2 2 6 2 3 2 2 2 2 2 2 2 2 6 2 3 if TEST e 0 Format 80C186EC Clock Cycles 80C188EC Clock Cycles Comments Shaded areas indicate instructions not available in 8086 8088 microsystems NOTE Clock cycles shown for byte transfers for word operations add 4 clock cycles for all memory transfers The Effective Address (EA) of the memory operand is computed according to the mod and r m fields if mod e 11 then r m is treated as a REG field if mod e 00 then DISP e 0 disp-low and disphigh are absent if mod e 01 then DISP e disp-low sign-extended to 16-bits disp-high is absent if mod e 10 then DISP e disp-high disp-low if r m e 000 then EA e (BX) a (SI) a DISP if r m e 001 then EA e (BX) a (DI) a DISP if r m e 010 then EA e (BP) a (SI) a DISP if r m e 011 then EA e (BP) a (DI) a DISP if r m e 100 then EA e (SI) a DISP if r m e 101 then EA e (DI) a DISP if r m e 110 then EA e (BP) a DISP if r m e 111 then EA e (BX) a DISP DISP follows 2nd byte of instruction (before data if required) except if mod e 00 and r m e 110 then EA e disp-high disp-low EA calculation time is 4 clock cycles for all modes and is included in the execution times given whenever appropriate Segment Override Prefix 0 0 1 reg 1 1 0 reg is assigned according to the following Segment reg Register 00 ES 01 CS 10 SS 11 DS REG is assigned according to the following table 16-Bit (w e 1) 8-Bit (w e 0) 000 AX 000 AL 001 CX 001 CL 010 DX 010 DL 011 BX 011 BL 100 SP 100 AH 101 BP 101 CH 110 SI 110 DH 111 DI 111 BH The physical addresses of all operands addressed by the BP register are computed using the SS segment register The physical addresses of the destination operands of the string primitive operations (those addressed by the DI register) are computed using the ES segment which may not be overridden 56 80C186EC 188EC 80L186EC 188EC ERRATA An 80C186EC 80L186EC with a STEPID value of 0002H has no known errata A device with a STEPID of 0002H can be visually identified by noting the presence of an ``A'' or ``B'' alpha character next to the FPO number or the absence of any alpha character The FPO number location is shown in Figures 4 5 and 6 REVISION HISTORY This data sheet replaces the following data sheets 272072-003 272076-003 272332-001 272333-001 272373-001 272372-001 80C186EC 80C188EC 80L186EC 80L188EC SB80C188EC SB80L188EC SB80C186EC SB80L186EC 57 |
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